**************************************************************************
**									**
**			( MODEL M125CN )				**
**									**
**	SPICE PARAMETERS						**
**	MCNC 1.25 CMOS PROCESS						**
**	( NOMINAL )							**
**									**
**	NOTE:	IV data was obtained with PISCES and fit to SPICE 	**
**		models with the curve fitting program SUXES.		**
**									**
**	Scott Goodwin-Johansson, Gary Nifong	02/26/87		**
**									**
**************************************************************************

.model nenh nmos
+    Level=2            Ld=0.0u         Tox=225.000e-10
+    Nsub=1.066e+16     Vto=0.622490    Kp=6.326640E-05
+    Gamma=.639243      Phi=.31         Uo=1215.74
+    Uexp=4.612355e-2   Ucrit=174667    Delta=0.0
+    Vmax=177269        Xj=.9u          Lambda=0.0
+    Nfs=4.55168e+12    Neff=4.68830    Nss=3.000000E+10
+    Tpg=1.00000        Rsh=60          Cgso=2.89e-10
+    Cgdo=2.89e-10      Cj=3.27e-04     Mj=1.067
+    Cjsw=1.74e-10      Mjsw=.195

.model penh pmos
+    Level=2            Ld=.03000000u   Tox=225.000e-10  
+    Nsub=6.575441e+16  Vto=-0.63025    Kp=2.635440E-05
+    Gamma=0.618101     Phi=.541111     Uo=361.941
+    Uexp=8.886957e-02  Ucrit=637449    Delta=0.0
+    Vmax=63253.3       Xj=0.112799u    Lambda=0.    
+    Nfs=1.668437e+11   Neff=0.64354    Nss=3.000000E+10
+    Tpg=-1.00000       Rsh=150         Cgso=3.35e-10
+    Cgdo=3.35e-10      Cj=4.75e-04     Mj=.341
+    Cjsw=2.23e-10      Mjsw=.307

*
*
*




* eight bit adder circuit
/* full adder circuit */
.subckt cnand inputa inputb out vdd vss
ml1 s1 inputa vss vss nenh  l=3.0u w=14.0u ad=56.0p pd=36.0u as=56.0p ps=36.0u
ml2 vdd inputa out vdd penh l=3.0u w=28.0u ad=112.0p pd=64.0u as=112.0p ps=64.0u
ml3 s1 inputb out vss nenh l=3.0u w=14.0u ad=56.0p pd=36.0u as=56.0p ps=36.0u
ml4 vdd inputb out vdd penh l=3.0u w=28.0u ad=112.0p pd=64.0u as=112.0p ps=64.0u

.ends cnand
*
	/* half adder subcircuit */
.subckt halfadd ramp1 ramp2 s3 out vdd vss
xlt1 ramp1 ramp2 s3 vdd vss cnand
xlt2 s3 ramp2 s4 vdd vss cnand
xlt3 ramp1 s3 s5 vdd vss cnand
xlt4 s5 s4 out vdd vss cnand
.ends halfadd

	/* full adder subcircuit */
.subckt fulladd cin a1 b1 cout out vdd vss
xha1 a1 b1 c1 o1 vdd vss halfadd
xha2 o1 cin c2 out vdd vss halfadd
xna3 c1 c2 cout vdd vss cnand
clt1 out vss .05p
clt2 cout vss .05p
.ends fulladd

	/* add first two bits, cin = 0 */
xful1 cout8 a1 b1 cout1 out1 vdd 0 fulladd
	/* add second two bits plus carry cout1 */
xful2 cout1 a2 b2 cout2 out2 vdd 0 fulladd
	/* add third two bits plus cout2 */
xful3 cout2 a3 b3 cout3 out3 vdd 0 fulladd
	/* add fourth */
xful4 cout3 a4 b4 cout4 out4 vdd 0 fulladd
	/* add fifth  */
xful5 cout4 a5 b5 cout5 out5 vdd 0 fulladd
	/* add sixth */
xful6 cout5 a6 b6 cout6 out6 vdd 0 fulladd
	/* add seventh */
xful7 cout6 a7 b7 cout7 out7 vdd 0 fulladd
	/* add eight */
xful8 cout7 a8 b8 cout8 out8 vdd 0 fulladd
cout1 out1 vss 0.05p
cout2 out2 vss 0.05p
cout3 out3 vss 0.05p
cout4 out4 vss 0.05p
cout5 out5 vss 0.05p
cout6 out6 vss 0.05p
cout7 out7 vss 0.05p
cout8 out8 vss 0.05p
cout9 cout3 vss 0.05p