* DCVS Voter Single-Bit Block * 2um -> LAMBDA = 0.8um * ************************************************************************** ** ** ** ( MODEL Mosis2CW ) ** ** ** ** SPICE PARAMETERS ** ** Mosis 2 micron scalable n-well ** ** ( WORST ) ** ** ** ** Note: From corner spice decks for 2um VTI process. ** ** BSIM preferred to Spice level 2. Also see ** ** mosis memo regarding deltaW for effective ** ** width calculations. This model assumes ** ** worst case deltaL. ** ** ** ** -ravi, Feb 10, 1988 ** ** ** ************************************************************************** .model nenh nmos + Level=2 Ld=0.05u Tox=430.000e-10 + Nsub=1.0e+16 Vto=0.90 Uo=620.0 + Uexp=0.125 Ucrit=62000 Delta=1.4 + Vmax=51000 Xj=.15u Lambda=0.0 + Neff=4.00 Tpg=1.00000 Rsh=38 + Cgso=2.10e-10 Cgdo=2.10e-10 Cj=2.15e-04 + Mj=0.76 Cjsw=5.40e-10 Mjsw=0.30 + Pb=0.8 .model penh pmos + Level=2 Ld=0.05u Tox=430.000e-10 + Nsub=6.6e+15 Vto=-0.90000 Uo=240.0 + Uexp=0.29 Ucrit=86000 Delta=1.0 + Vmax=30000 Xj=0.050000u Lambda=0. + Neff=2.65000 Tpg=-1.00000 Rsh=110 + Cgso=2.05e-10 Cgdo=2.05e-10 Cj=2.75e-04 + Mj=.535 Cjsw=4.00e-10 Mjsw=.34 + Pb=0.8 * *************************************************************************** * * * LAMBDA for 2.0 -> 1.0u * *************************************************************************** * * * Standard DCVS LOAD * * * * * * vdd * * | * * +--------------+-------+-------+--------+------+-----------+ * * | | | | | | * * P3 |---+ | | PC | | +---| P4 * * | | | | | | | | | * * F0----+------------|P1 P5|-----+------|P6 P2|---------+---F1 * * | | | | | | | | * * NL1|---+ | | | | +---|NL2 * * | | | | | | | | * * | +-------+-------+ +------+-----+ | * * Vss | | Vss * * +--G1 G0---+ * * * * * *************************************************************************** * .subckt load vdd vss pc g1 g0 f1 f0 * * LOAD * leakage compensators MP1 vdd f0 g1 vdd penh l=6.0u w=3.0u /* 6x3 */ MP2 vdd f1 g0 vdd penh l=6.0u w=3.0u /* 6x3 */ * * Inverters MP3 vdd g1 f0 vdd penh l=2.0u w=16.0u /* 2x16 */ MNL1 f0 g1 vss vss nenh l=2.0u w=6.0u /* 2x6 */ MP4 vdd g0 f1 vdd penh l=2.0u w=16.0u /* 2x16 */ MNL2 f1 g0 vss vss nenh l=2.0u w=6.0u /* 2x6 */ * * Precharge MP5 vdd pc g1 vdd penh l=2.0u w=4.0u /* 2x4 */ MP6 vdd pc g0 vdd penh l=2.0u w=4.0u /* 2x4 */ * .ends load * * *************************************************************************** * DCVS Voter Error Correction Block * * * This circuit models a error correction block. By permuting the * * inputs to a set of instantiations of this block, the complete * * error correction logic (minus I/O buffers) may be implemented. * * * * F(X,X',Y,Y',Z,Z') = Majority(X,Y,Z) * * = XYZ + X'YZ + XY'Z + XYZ' * * * * * * +--G1 G0---+ * * | | * * | +--------+-----+ * * | | | * * +-----------+--------+ | | * * | | | | * * | X0----|N5 X1--|N6 | * * | | | | * * | +------+------+ | * * | | d | | * * Y0----|N1 Y1----|N3 N7|--Y0 N9|---Y1 * * | | | | * * +--------------------+f g+--------------+ * * | | * * Z0----|N4 N8|--Z1 * * | e | * * +---+---------+ * * | * * N20|---PC * * | * * Vss * * * * * *************************************************************************** * * .subckt cblk vdd vss pc x1 x0 y1 y0 z1 z0 f1 f0 * LOAD xload vdd vss pc g1 g0 f1 f0 load * * NMOS Tree * * Precharge MN_pc e pc vss vss nenh l=2.0u w=8.0u /* 2x8 */ * * 0-loop MN1 g1 y0 f vss nenh l=2.0u w=3.0u /* 2x3 */ * * 1-loop MN9 g0 y1 g vss nenh l=2.0u w=3.0u /* 2x3 */ * * 10-loop MN5 g1 x0 d vss nenh l=2.0u w=3.0u /* 2x3 */ MN6 g0 x1 d vss nenh l=2.0u w=3.0u /* 2x3 */ MN3 d y1 f vss nenh l=2.0u w=5.0u /* 2x5 */ MN7 d y0 g vss nenh l=2.0u w=5.0u /* 2x5 */ MN4 f z0 e vss nenh l=2.0u w=6.0u /* 2x6 */ MN8 g z1 e vss nenh l=2.0u w=6.0u /* 2x6 */ .ends cblk * * * *************************************************************************** * DCVS Voter Fault Detection Block * * * This circuit is models a fault detection block. By permuting the * * inputs to a set of instantiations of this block, the complete * * fault detection logic (minus I/O buffers) may be implemented. * * * * F(X,Y,Z) = '1' --> Signal X is faulty * * * * F(X,Y,X) = (X^Y)(X^Z)(Y==Z) * * = XY'Z' + X'YZ * * * * * * +--G1 G0---+ * * | | * * | +--------+--------+ * * | | | * * +---+--------+--------------------+----------|-------+ * * | | | | | | * * | X0----|N5 X1----|N6----|N9 N10|--X0 | * * | | c | | d | | * * | +------+------+ +----+-----+ | * * | | | | * * Y1----|N1 N7|--Y0 N11|---Y1 N2|---Y0 * * | | | | * * +-------------------+f g+-------------+ * * | | * * N8|--Z0 N12|---Z1 * * | | * * e+------------------+ * * | * * N20|---PC * * | * * Vss * * * * * *************************************************************************** * .subckt fblk vdd vss pc x1 x0 y1 y0 z1 z0 f1 f0 * * LOAD xload vdd vss pc g1 g0 f1 f0 load * * NMOS Tree * * Precharge MN20 e pc vss vss nenh l=2.0u w=8.0u /* 2x8 */ * * 0-loop MN1 g1 y1 f vss nenh l=2.0u w=3.0u /* 2x3 */ MN2 g1 y0 g vss nenh l=2.0u w=3.0u /* 2x3 */ * * 01-loop MN5 g1 x0 c vss nenh l=2.0u w=3.0u /* 2x3 */ MN6 g0 x1 c vss nenh l=2.0u w=3.0u /* 2x3 */ MN7 c y0 f vss nenh l=2.0u w=4.0u /* 2x4 */ MN8 f z0 e vss nenh l=2.0u w=6.0u /* 2x6 */ * * 10-loop MN9 g1 x1 d vss nenh l=2.0u w=3.0u /* 2x3 */ MN10 g0 x0 d vss nenh l=2.0u w=3.0u /* 2x3 */ MN11 d y1 g vss nenh l=2.0u w=4.0u /* 2x4 */ MN12 g z1 e vss nenh l=2.0u w=6.0u /* 2x6 */ * .ends fblk * * *************************************************************************** * * * TWO-INPUT XOR .subckt exor2 vdd vss pc x xbar y ybar f fbar xload vdd vss pc g1 g0 f fbar load * MN_pc e pc vss vss nenh l=2.0u w=4.8u /* 2x6 */ * MN1 g0 xbar a vss nenh l=2.0u w=3.2u /* 2x4 */ MN2 g1 x a vss nenh l=2.0u w=3.2u /* 2x4 */ MN3 g1 xbar b vss nenh l=2.0u w=3.2u /* 2x4 */ MN4 g0 x b vss nenh l=2.0u w=3.2u /* 2x4 */ * MN5 a y e vss nenh l=2.0u w=4.0u /* 2x5 */ MN6 b ybar e vss nenh l=2.0u w=4.0u /* 2x5 */ .ends exor2 * * * THREE-INPUT XOR .subckt exor3 vdd vss pc x xbar y ybar z zbar f fbar xload vdd vss pc g1 g0 f fbar load * MN_pc e pc vss vss nenh l=2.0u w=5.6u /* 2x7 */ * MN1 g0 xbar a1 vss nenh l=2.0u w=3.2u /* 2x4 */ MN2 g1 x a1 vss nenh l=2.0u w=3.2u /* 2x4 */ MN3 g1 xbar a0 vss nenh l=2.0u w=3.2u /* 2x4 */ MN4 g0 x a0 vss nenh l=2.0u w=3.2u /* 2x4 */ * MN5 a1 y b1 vss nenh l=2.0u w=4.0u /* 2x5 */ MN6 a0 ybar b1 vss nenh l=2.0u w=4.0u /* 2x5 */ MN7 a0 y b0 vss nenh l=2.0u w=4.0u /* 2x5 */ MN8 a1 ybar b0 vss nenh l=2.0u w=4.0u /* 2x5 */ * MN9 b1 zbar e vss nenh l=2.0u w=4.8u /* 2x6 */ MN10 b0 z e vss nenh l=2.0u w=4.8u /* 2x6 */ .ends exor3 * * FOUR-INPUT XOR .subckt exor4 vdd vss pc w wbar x xbar y ybar z zbar f fbar xload vdd vss pc g1 g0 f fbar load * MN_pc e pc vss vss nenh l=2.0u w=6.4u /* 2x8 */ * MN1 g0 wbar a1 vss nenh l=2.0u w=2.4u /* 2x3 */ MN2 g1 w a1 vss nenh l=2.0u w=2.4u /* 2x3 */ MN3 g1 wbar a0 vss nenh l=2.0u w=2.4u /* 2x3 */ MN4 g0 w a0 vss nenh l=2.0u w=2.4u /* 2x3 */ * MN5 a1 x b1 vss nenh l=2.0u w=3.2u /* 2x4 */ MN6 a0 xbar b1 vss nenh l=2.0u w=3.2u /* 2x4 */ MN7 a0 x b0 vss nenh l=2.0u w=3.2u /* 2x4 */ MN8 a1 xbar b0 vss nenh l=2.0u w=3.2u /* 2x4 */ * MN9 b1 y c1 vss nenh l=2.0u w=4.0u /* 2x5 */ MN10 b0 ybar c1 vss nenh l=2.0u w=4.0u /* 2x5 */ MN11 b0 y c0 vss nenh l=2.0u w=4.0u /* 2x5 */ MN12 b1 ybar c0 vss nenh l=2.0u w=4.0u /* 2x5 */ * MN13 c1 z e vss nenh l=2.0u w=5.6u /* 2x7 */ MN14 c0 zbar e vss nenh l=2.0u w=5.6u /* 2x7 */ .ends exor4 * * EIGHT-INPUT XOR .subckt exor8 vdd vss pc + a0 a0bar a1 a1bar a2 a2bar a3 a3bar + a4 a4bar a5 a5bar a6 a6bar a7 a7bar + f fbar xexor1 vdd vss pc a0 a0bar a1 a1bar a2 a2bar a3 a3bar f1 f1bar exor4 xexor2 vdd vss pc a4 a4bar a5 a5bar a6 a6bar a7 a7bar f2 f2bar exor4 xexor3 vdd vss pc f1 f1bar f2 f2bar f fbar exor2 .ends exor8 * * *************************************************************************** * * DCVS OR GATES * LAMBDA for 2.0 -> 0.8u * * TWO-INPUT OR .subckt or2 vdd vss pc a abar b bbar f fbar *.subckt load vdd vss pc g1 g0 f1 f0 xload vdd vss pc g1 g0 f fbar load * MN_pc e pc vss vss nenh l=2.0u w=3.2u /* 2x4 */ * MN1 g1 abar n2 vss nenh l=2.0u w=3.2u /* 2x4 */ MN2 n2 bbar e vss nenh l=2.0u w=3.2u /* 2x4 */ * MN3 g0 a e vss nenh l=2.0u w=3.2u /* 2x4 */ * MN4 g0 abar n5 vss nenh l=2.0u w=3.2u /* 2x4 */ MN5 n5 b e vss nenh l=2.0u w=3.2u /* 2x4 */ .ends or2 * * THREE-INPUT OR .subckt or3 vdd vss pc a abar b bbar c cbar f fbar xload vdd vss pc g1 g0 f fbar load * MN_pc e pc vss vss nenh l=2.0u w=4.8u /* 2x6 */ * MN1 g1 abar n2 vss nenh l=2.0u w=3.2u /* 2x4 */ MN2 n2 bbar n3 vss nenh l=2.0u w=3.2u /* 2x4 */ MN3 n3 cbar e vss nenh l=2.0u w=3.2u /* 2x4 */ * MN5 g0 a e vss nenh l=2.0u w=3.2u /* 2x4 */ MN6 g0 abar n7 vss nenh l=2.0u w=3.2u /* 2x4 */ MN7 n7 b e vss nenh l=2.0u w=3.2u /* 2x4 */ MN8 n7 bbar n9 vss nenh l=2.0u w=3.2u /* 2x4 */ MN9 n9 c e vss nenh l=2.0u w=3.2u /* 2x4 */ .ends or3 * * FOUR-INPUT OR .subckt or4 vdd vss pc a abar b bbar c cbar d dbar f fbar xload vdd vss pc g1 g0 f fbar load * MN_pc e pc vss vss nenh l=2.0u w=6.4u /* 2x8 */ * MN1 g1 abar n2 vss nenh l=2.0u w=3.2u /* 2x4 */ MN2 n2 bbar n3 vss nenh l=2.0u w=3.2u /* 2x4 */ MN3 n3 cbar n4 vss nenh l=2.0u w=3.2u /* 2x4 */ MN4 n4 dbar e vss nenh l=2.0u w=3.2u /* 2x4 */ * MN5 g0 a e vss nenh l=2.0u w=3.2u /* 2x4 */ MN6 g0 abar n7 vss nenh l=2.0u w=3.2u /* 2x4 */ MN7 n7 b e vss nenh l=2.0u w=3.2u /* 2x4 */ MN8 n7 bbar n9 vss nenh l=2.0u w=3.2u /* 2x4 */ MN9 n9 c e vss nenh l=2.0u w=3.2u /* 2x4 */ MN10 n9 cbar n11 vss nenh l=2.0u w=3.2u /* 2x4 */ MN11 n11 d e vss nenh l=2.0u w=3.2u /* 2x4 */ .ends or4 * * EIGHT-INPUT OR .subckt or8 vdd vss pc + a0 a0bar a1 a1bar a2 a2bar a3 a3bar + a4 a4bar a5 a5bar a6 a6bar a7 a7bar + f fbar xor1 vdd vss pc a0 a0bar a1 a1bar a2 a2bar a3 a3bar f1 f1bar or4 xor2 vdd vss pc a4 a4bar a5 a5bar a6 a6bar a7 a7bar f2 f2bar or4 xor3 vdd vss pc f1 f1bar f2 f2bar f fbar or2 .ends or8 * *************************************************************************** *************************************************************************** * * SINGLE-BIT VOTER .subckt bit_voter + vdd vss phi1 + a0 a0_bar b0 b0_bar c0 c0_bar + data data_bar + error_a error_abar + error_b error_bbar + error_c error_cbar xcblk0 + vdd vss phi1 + a0 a0_bar b0 b0_bar c0 c0_bar + data data_bar + cblk xfblk0_a + vdd vss phi1 + a0 a0_bar b0 b0_bar c0 c0_bar + error_a error_abar + fblk xfblk0_b + vdd vss phi1 + b0 b0_bar c0 c0_bar a0 a0_bar + error_b error_bbar + fblk xfblk0_c + vdd vss phi1 + c0 c0_bar a0 a0_bar b0 b0_bar + error_c error_cbar + fblk .ends bit_voter * * *************************************************************************** *************************************************************************** * xbit_voter0 + vdd vss phi1 + a0 a0_bar b0 b0_bar c0 c0_bar + data data_bar + error_a error_abar + error_b error_bbar + error_c error_cbar + bit_voter